Emulation systems may include hardware components inclusive of processor-based (i.e., hardware-based) emulation chips. By executing various forms of programmable logic on the processor-based emulation chips, the emulation chips may be designed to mimic the functionality of nearly any ASIC or logic system design that is undergoing testing. Such hardware emulation systems may include hundreds or thousands of processors that collectively simulate the functionality of a logic system. In many cases, these ASICs may be synchronous ASICs. As understood in the art, the cost of building an ASIC is very expensive, so using an emulation system is a much less expensive and more reliable way of verifying a logic system before building an ASIC. As further understood in the art, emulators may also be software-based, but software simulations are significantly slower than hardware emulators.
Because of the complexity of hardware-based emulation systems, however, the ability to control and manage development of virtual logic (i.e., emulated hardware of an ASIC being designed and tested by the hardware of the hardware-based emulation system) is a way for the designer (i) to ensure synchronization of each of the chips that are to be synchronized during an emulation, and (ii) to test and debug the virtual logic. Historically, the use of field programmable gate arrays (FPGAs) that were positioned in control paths were used for managing synchronization of emulation testing devices and debugging of the virtual logic being emulated. As understood in the art, the FPGAs were preprogrammed as desired to handle desired control of hardware and signaling in the emulator, and programming the FPGAs allowed for easy control of the emulator to handle the synchronization, testing, and debugging. However, with an emulator design that does not include FPGAs positioned in the control or data paths due to not using FPGAs throughout the hardware-based emulator, there is no ability to provide for synchronization of emulation devices and testing and debugging of the virtual logic on the hardware-based emulator. Accordingly, there is a need to provide for the ability to synchronize emulation devices and test and debug virtual logic on a hardware-based emulator without an FPGA in control and data paths of the emulator.